1. Field of the Invention
This invention relates generally to the manufacture method for semiconductor chips and integrated circuits (ICs). More particularly, this invention relates to a novel and improved method of manufacture by applying a differentiating polishing technique on the top layer of the semiconductor chip to produce a variation of polishing rates of these layers such that the variations of rates are proportional to the profile heights in different areas for layer removal such that the planarization process can be precisely controlled and effectively carried out with a simplified and cost-effective methodology.
2. Description of the Prior Art
The planarization process for producing a smooth planar surface on the top surface of a semiconductor chip still faces technical difficulties that more complicate processing steps are required to achieve a non-dishing surface profile. The major difficulties arise from the fact that different areas on the top surface usually have different profile heights rising above the substrate. In order to produce a leveled planarized surface, removal of layers near the top surface of different thickness in different areas, depending on the profile, would be required in order to produce a truly planar surface. However, it is often difficult to differentiate and then precisely control the polishing and layer removal processes in different areas to remove the top layers at different rates in order to achieve this planarization purpose. Various techniques are applied to circumvent this difficulties as will be discussed below. However, these techniques are often quite complicated, requiring the applications of more processing steps and thus unduly increasing the time and cost of production in manufacturing the semiconductor chips.
The "dishing effect" resulting from a conventional planarization process can be understood by referring to the cross section views shown in FIGS. 1A to 1C where a semiconductor chip 10 of wide spacing 15 is disposed between two circuit elements 12 and 14 raising above a planar surface. FIG. 1A shows a silicon dioxide layer 20 is formed covering over the top of the circuit elements and the wide spacing 15. Conforming to the profile formed by the circuit elements 12, 14 and the wide spacing 15 between them, the top surface of the oxide layer 20 above the wide spacing 15 parallel substantially to top surface of the substrate 11 steps to a lower level 16. In FIG. 2, a polishing pad layer 25 is then deposited on top of the silicon dioxide layer 20. The polishing pad layer 25 is then polished by the use of a chemical mechanical polishing (CMP) process to generate a planar surface. FIG. 1C shows the polished surface which has a dishing depressions 24 right over the top correspond to the edges where the circuit elements 12 and 14 defining the boundary of the wide spacing 15.
In order to prevent this dishing profile as shown in FIG. 1C, a two-step chemical-mechanical polishing (CMP) process is applied. In this two step CMP process, a polishing stopper layer is deposited on top of the dielectric layer, e.g., layer 20 as shown in FIG. 1B. An example of such polishing stopper is a polyimide layer. In this two-step CMP process, a polishing stopper layer, e.g., a polyimide layer, is deposited on top of the dielectric layer. A photolithography process is performed on the polishing stopper carbon layer. The polishing layer is then etched to form the polishing stopper. A first CMP is performed to remove the portion of the dielectric layer such that a level surface is formed at a same level as that of the polishing stopper. The polishing stopper is then removed and a second CMP process is carried out to planarize the dielectric layer.
While the two step Cow process, as described above, can provide the advantage that a dishing profile on a semiconductor chip is eliminated with depressions on the top surface removed. However, compared to the one-step CMP process illustrated in FIGS. 1A to 1C, this two-step CMP process is more complicate which involves more processing steps thus is more time consuming and also causing the cost of manufacture to increase.
A different technique to prevent the dishing effect on a surface of the semiconductor chip which usually occur in patterned wide spacing between circuit elements, is to form dummy pattern in the wide spacing areas to eliminate the wide spacing, e.g., wide spacing 15 as that shown in FIG. 1A. With the dummy patterns formed on the wide spacing areas, a semiconductor chip can be planarized with a one-step CMP process. However, the circuit RC delay caused by resistor-capacitor (RC) effect is increased when dummy patterns are added in the wide spacing areas. The speed of circuit operation and performance level are often adversely affected with the dummy patterns added for the purpose of chip planarization.
Therefore, a need still exists in the art of semiconductor chip and integrated circuit (IC) manufacture to provide a novel manufacture process to resolve the above difficulties. It is desirable that the novel manufacture process is simple and easy to implement whereby a lower cost of manufacture can be achieved . Additionally, it is desirable that this novel manufacture process provides more control precision for the planarization process such that high quality leveled planar surface of a semiconductor chip can be produced reliably and the quality, reliability, and performance level of integrated circuits forming in the semiconductor chips can be improved.